1. Field of the Invention
The present invention relates to a fabrication method of a self-aligned ferroelectric gate transistor and, more particularly, to a fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity to improve a chip density without damage to a silicon substrate.
2. Description of the Background Art
A conventional fabrication method of a ferroelectric gate transistor is as follows.
First, source and drain regions are formed in a silicon substrate, on which a thin film layer with high oxidizing power is formed, on which a ferroelectric layer and an electrode layer are formed sequentially, resulting in a stacked structure consisting of silicon/thin film layer/ferroelectric layer/electrode layer.
The reason for formation of the thin film layer with high oxidizing power on the silicon substrate is to prevent degradation of operational characteristics of the ferroelectric due to a SiO2 thin film formed at the interface of the ferroelectric and silicon. In other words, during the process of fabrication of the self-aligned ferroelectric gate transistor, generally, the SiO2 thin film is undesirably formed at the interface of the ferroelectric and silicon to degrade operational characteristics of the ferroelectric. Thus, by forming the thin film layer with high oxidizing power on the silicon substrate, formation of the SiO2 thin film can be restrained because the thin film layer has a stronger bonding force with oxygen than silicon.
Next, with the resulting stacked structure, the electrode layer and the ferroelectric layer corresponding to the source and drain regions are wet-etched for metal wiring.
However, such a conventional fabrication method has the following problem.
That is, for example, due to the misalign in a photo process, a margin overlapped between the source/gate and drain/gate should be provided. Also, since the areas of the source and drain are enlarged due to the wet etching, integration degree of the ferroelectric gate transistor cannot be enhanced.
Thus, in order to enhance the integration degree, the self-alignment gate process currently adopted for the CMOS process needs to be applied to the ferroelectric gate transistor.
A dry etching is performed in the self-alignment gate process. However, when the ferroelectric layer and thin film layer are dry-etched, silicon is also etched due to a low etching selectivity, causing a problem that the surface of silicon is much damaged.